The ever-increasing need for greater bandwidth in core, enterprise, and local-area networks has driven the popular Institute for Electrical and Electronic Engineers (IEEE) 802.3 Ethernet standard to continuously push the transmission speeds for simple, low-cost, point-to-point networking. As transmission rates increase, the design of the Physical Layer protocols dramatically impacts the cost and complexity of both component and system implementation.
Beginning with the Fast Ethernet standard (IEEE 802.3u), the physical layer was partitioned into several sublayers, each of which encapsulates largely independent functionality. The Physical Coding Sublayer (PCS) is responsible for frame delineation, frame formatting, and line coding. Key characteristics of the PCS for high-speed transmission are that it should 1) offer a low-overhead, robust frame delineation; 2) utilize a low-overhead data encoding that does not unnecessarily burden front-end receiver circuitry; 3) be amenable to implementation in commodity silicon technology; and 4) take into account system-level implementation and integration issues such as electromagnetic interference mitigation.
In the so-called Gigabit Ethernet Standard (IEEE 802.3z), an 8 b/10b block code is used for both line coding and frame delineation. The 8b/10b coding scheme offers several desirable properties, namely a large code space having many unused codes (so that errors are reliably detected), good transition density, run-length limiting and DC-balancing. These advantages are offset by the 25% overhead. For example, for serial transmission at a bit rate of 10 Gbits/s, the 25% overhead of 8 b/10 b coding requires optical and electrical components that operate at 12.5 GHz. Currently, components with this capability are neither low cost nor manufacturable in high volume and yield. Further, the deterministic nature of the block code gives rise to serious electromagnetic interference (EMI) generation when the input symbol stream is constant or highly repetitive, as is the case when the link is idle and long sequences of IDLE characters are transmitted.
An improved point-to-point data link protocol is described by Doshi et al. in an article entitled “A Simple Data Link Protocol for High-Speed Packet Networks,” published in the Bell Labs Technical Journal January–March 1999 on pages 85–104 and incorporated herein by reference in its entirety. The described simple data link (SDL) protocol provides for the framing of asynchronous protocol data units (PDUs) using a length indicator and pointer scheme whereby a pointer in the header of one packet or data frame is used to identify the start of a next packet or data frame. The SDL utilizes a length indicator field and a header cyclic redundancy check (CRC) to delineate frames. Unfortunately, in the case where packet length information is not available, an entire packet must be stored, thereby increasing latency. This may not be acceptable in some applications, such as “cut-through” packet switching.